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Texas Instruments SN65LVDS117DGGR — Interface & Transceivers

SN65LVDS117DGGR LVDS Buffer/Mux, 400Mbps, 64-TSSOP

MPNSN65LVDS117DGGR
Active

Texas Instruments SN65LVDS117DGGR LVDS Buffer, Multiplexer, 1 x 2:16, 400Mbps, 2.8ns delay, 3V-3.6V supply, 64-TFSOP (6.10mm Width) Tape & Reel.

$12.0600Ref. price · indicative, final on quote
Packaging64-TFSOP (0.240", 6.10mm Width)
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

SN65LVDS117DGGR specifications
ParameterValue
TypeBuffer, Multiplexer
MountingSurface Mount
Supply voltage3V ~ 3.6V
Current - supply85mA
Operating temperature-40°C~85°C
InputLVDS
OutputLVDS
PackageTape & Reel (TR); Cut Tape (CT)
Delay time2.8ns
Case64-TFSOP (0.240\", 6.10mm Width)
Data rate400Mbps
Channels1 x 2:16
Capacitance - input5 pF

Product details

Active-production 1:16 LVDS fanout with 400 Mbps throughput

The SN65LVDS117DGGR: Rated for 400 Mbps per channel with a 2.8 ns propagation delay, it distributes high-speed clock or data across a backplane without retiming. The 5 pF input capacitance keeps the load on the source driver low, preserving signal integrity at the fan-out root.

Supply rails, temperature grade, and package for board integration

Housed in a 64-TFSOP package (6.10 mm body width) with a 64-TSSOP supplier device package. Surface-mount assembly on a standard 0.50 mm pitch TSSOP footprint; the narrow body width fits dense PCB layouts where board real estate is a constraint.

Sourcing reality and cross-reference context

Sourced through independent distribution channels against an RFQ. The DS25BR101TSDE/NOPB is a 3.125 Gbps LVDS buffer with input equalisation and output pre-emphasis, but it is a single-channel redriver in a smaller package — not a 1:16 fan-out mux. A board designed for the SN65LVDS117DGGR's 64-TSSOP footprint and 1:16 topology cannot drop in the DS25BR101 without a layout and logic redesign.

Frequently asked questions

What is the data rate and propagation delay of the SN65LVDS117DGGR?

The part supports a maximum data rate of 400 Mbps with a 2.8 ns typical propagation delay. This makes it suitable for distributing high-speed LVDS clock or data signals across multiple destinations without retiming.