1:2:16 LVDS fanout — what the channel count and data rate mean for the link
The SN65LVDS117DGGG4 is a Texas Instruments LVDS buffer and multiplexer that takes one differential LVDS input and fans it out to sixteen LVDS outputs in a 1:2:16 topology. This is a single-chip solution for distributing a high-speed serial clock or data stream across multiple receiver nodes on a backplane or cable interconnect, without the skew and signal-integrity degradation of a passive split. The 400 Mbps per-channel data rate covers common LVDS link speeds for video interfaces, base station clock distribution, and test equipment front-ends, while the 2.8 ns propagation delay keeps lane-to-lane skew tight enough for most parallel LVDS busses.
64-TSSOP package — layout and procurement notes
Housed in a 64-TSSOP (0.240", 6.10 mm width) surface-mount package, the part requires a fine-pitch PCB footprint typical of high-density digital logic. The 5 pF input capacitance is low enough that it does not load the upstream LVDS driver beyond its specified fanout.
TI lists the SN65LVDS117DGGG4 as Active (current production). For dual-sourcing resilience, the base product number 65LVDS117 covers multiple speed and package variants; a pin-compatible sibling in the same family would share the same footprint and supply range, but no official cross-reference is cited here. If you need a validated second source, request a cross-reference from your distributor against the full 65LVDS117 family.