1:16 LVDS fanout buffer — 400 Mbps, 3.1 ns delay
The Texas Instruments SN65LVDS116DGGR is a 1:16 LVDS buffer and multiplexer designed to distribute one LVDS input to sixteen LVDS outputs. It is commonly used in backplane clock distribution, cable interconnect fanout, and test equipment where one LVDS signal must drive multiple loads cleanly.
The 400 Mbps per-channel data rate sets the maximum serial bitstream the part can cleanly retransmit. At this speed the 3.1 ns propagation delay contributes roughly 1.2 unit intervals of skew in a parallel bus, so the designer needs to budget that into the timing closure for the receiving LVDS deserializer. The 5 pF input capacitance is low enough that a single upstream driver can feed the buffer without extra line conditioning at 400 Mbps.
The base product number 65LVDS116 covers the family; the DGGR suffix denotes the 64-TSSOP package and tape-and-reel shipping form.