Active 1:8 LVDS fanout buffer/mux for backplane and clock distribution
The Texas Instruments SN65LVDS109DBTG4 is a 1 x 2:8 LVDS buffer and multiplexer in a 38-pin TSSOP package. It takes one of two LVDS input pairs and fans out to eight LVDS output pairs, with a maximum data rate of 400 Mbps per channel and a typical propagation delay of 2.8 ns.
400 Mbps per channel — what the rate means for the link budget
The 400 Mbps data rate is the per-channel ceiling for NRZ signalling. At this speed, the 2.8 ns propagation delay contributes roughly 1.1 UI of skew budget — a factor when daisy-chaining multiple fanout stages or distributing a clock across a backplane. The input capacitance of 5 pF loads the upstream driver; a source with 50 Ω output impedance and 3.3 V swing will see a 250 ps edge-rate degradation from this load, which is manageable below 400 Mbps but tightens margin at the upper end.
The base product number 65LVDS109 spans multiple package and temperature variants, but this DBTG4 suffix (38-TSSOP, RoHS) remains the standard production code.