1:8 LVDS fanout buffer — what the 400 Mbps and 2.8 ns delay mean for the bus
The Texas Instruments SN65LVDS108DBTG4 is a 1:8 LVDS buffer and multiplexer that takes one differential LVDS input and delivers it to eight LVDS outputs. The 400 Mbps per-channel data rate supports high-speed serial links such as backplane clock distribution, video data fanout, or multi-drop bus repeaters. The 2.8 ns propagation delay is the key timing parameter: it sets the minimum skew budget when the part is used in a clock tree or parallel data path. At 400 Mbps the unit interval is 2.5 ns, so the 2.8 ns delay means the output transitions arrive one full bit period later — account for this in the receive-side setup/hold window. Input capacitance is 5 pF, light enough to not load the upstream driver excessively.
For new designs this means no forced redesign cycle from a looming discontinuation.
Package and temperature grade — 38-TSSOP, industrial range
Housed in a 38-TFSOP (4.40 mm width) surface-mount package, the supplier device package is 38-TSSOP. No special bake or handling beyond standard MSL precautions is required for this package family.