1:4 LVDS fanout with mux — what the specs mean for the BOM
The SN65LVDS105PWR is a 1 x 1:4 LVDS buffer and multiplexer from Texas Instruments. It takes a single LVTTL input and fans it out to four LVDS outputs, running up to 400 Mbps per channel. The 2.2 ns propagation delay sets the timing budget for the receiving end — at 400 Mbps the bit period is 2.5 ns, so the delay consumes about 88% of the UI, leaving roughly 0.3 ns of margin before the next clock edge. That is tight; keep the trace length short and the load capacitance at or below the 3 pF input spec to avoid eating into the remaining window. The 1:4 fanout means a single source drives four downstream receivers without rebuffering — useful for clock distribution or data fanout on a backplane where the trace stubs would otherwise degrade signal integrity.
Package and rework — 16-TSSOP on the bench
The surface-mount footprint fits a standard 16-TSSOP land pattern.
The 85°C ceiling is the standard industrial limit; if the junction temperature stays below 125°C in the application, the part operates within its SOA without derating.