What this LVDS buffer/multiplexer does and where it goes
The Texas Instruments SN65LVDS105PWG4 is a 1:4 LVDS buffer and multiplexer that takes a single LVTTL input and fans it out to four LVDS outputs. It is designed for high-speed signal distribution in backplanes, cable interconnects, and clock/data fanout applications where signal integrity over twisted-pair or PCB traces matters.
400 Mbps data rate and 2.2 ns delay — timing budget reality
At 400 Mbps the bit period is 2.5 ns, so the 2.2 ns propagation delay consumes nearly 90% of one unit interval. That means this part works cleanly in a single-stage fanout but cascading multiple buffers will close your timing margin fast. The 3 pF input capacitance is low enough that a single LVTTL source can drive it without extra buffering, but the total load on the source is the sum of the input cap plus the trace parasitics.
Industrial temperature rating and supply range
Note that the input is LVTTL only; 5 V logic inputs will exceed the absolute maximum ratings, so a 5 V-tolerant input is not supported.
Package and footprint — 16-TSSOP
Housed in a 16-TSSOP (4.40 mm width) with a surface-mount footprint.