At 400 Mbps the SN65LVDS105DR can serialize a 40 MHz parallel bus into a single LVDS pair, or distribute a 200 MHz clock with sub-3 ns edge-to-edge skew across four outputs. The 2.2 ns propagation delay is the time from input crossing to output valid; in a clock tree this adds to the overall skew budget, so if you are fanning out a 100 MHz clock to multiple receivers, account for the delay mismatch between this buffer and any other devices in the path. The 3 pF input capacitance is light enough that a single LVTTL source can drive it without extra buffering.
Supply rails and signal levels
The LVTTL input threshold is compatible with 3.3 V logic families; the LVDS output delivers a differential swing of roughly 350 mV into a 100 Ω termination, standard for LVDS receivers. No external bias resistors needed on the output side — the driver handles the common-mode voltage internally.