What this LVDS buffer/repeater does
It's designed to clean up and re-drive high-speed differential signals over longer PCB traces or cables, compensating for signal degradation from attenuation and reflections. Input capacitance is 3 pF, which keeps the loading light on the driving source.
400 Mbps data rate and 1.7 ns delay — timing budget considerations
The 400 Mbps maximum data rate means each channel can carry a 200 MHz clock or a 400 Mbps serial data stream. The 1.7 ns propagation delay adds to the total link latency; in a multi-drop or daisy-chain topology with several reDrivers in series, the accumulated delay can eat into setup-and-hold margins. For a single reDriver stage, 1.7 ns is tight enough for most backplane and cable-extension applications at 400 Mbps, but if you're cascading multiple devices, budget the delay per hop. The 3 pF input capacitance is low enough that it won't significantly load the upstream driver's output stage, even at these speeds.
RoHS compliance is standard for this TI family.