400 Mbps dual-channel LVDS buffer — signal conditioning for high-speed links
It accepts LVDS or LVTTL inputs and delivers LVDS or LVTTL outputs, making it a flexible signal-conditioning block for backplane, cable, and clock distribution applications.
400 Mbps data rate and 1.7 ns delay — timing budget for the bus
The 400 Mbps maximum data rate handles most parallel LVDS links, including 24-bit video, high-speed ADC data, and backplane control buses. The 1.7 ns propagation delay is tight enough to fit into most clock distribution trees without eating into setup-and-hold margins. When cascading multiple buffers, add the delay per stage to your total skew budget — at 1.7 ns per device, a three-stage chain adds about 5.1 ns of latency.
For new designs, this means standard distribution availability and no forced redesign cycle.
16-TSSOP — footprint for dense PCB layouts
The 1.27 mm pitch is standard for hand-assembly and automated pick-and-place. The supplier device package is 16-TSSOP, matching the package/case code.