400 Mbps LVDS fanout — why the 1:4 ratio matters
The Texas Instruments SN65LVDS104PWRG4 is a 1 x 1:4 LVDS buffer and multiplexer that takes one differential LVDS input and delivers four identical LVDS outputs. It handles serial data streams up to 400 Mbps per channel, with a propagation delay of 3.1 ns. The part is built for clock or data fanout in high-speed backplanes, cable extenders, and test equipment where signal integrity over a point-to-point LVDS link needs to be preserved across multiple loads.
3.1 ns delay — timing budget for matched routes
The 3.1 ns propagation delay is the time from input crossing to output crossing. In a clock distribution tree, that delay adds to the overall skew budget, so you'll want to match trace lengths from the SN65LVDS104PWRG4 outputs to the receivers to keep intra-pair skew under a few hundred picoseconds. The 3 pF input capacitance is light enough that a single upstream driver can feed the buffer without re-drive.