Single-channel signal conditioner for high-speed serial links
It is designed for serial links where the signal has degraded over a backplane or cable — the device reshapes the waveform and re-drives it without retiming, adding only 630 ps of propagation delay. Typical deployment is in telecom infrastructure, base stations, and high-speed data-acquisition systems where a 2 Gbps data rate must be maintained across a few metres of FR4 or a connector.
Input protocol flexibility and output standard
The input stage handles three common differential signalling standards — CML, LVDS, and LVPECL — without external level-shifting resistors. This makes the SN65LVDS101DR a universal buffer for mixed-protocol environments: a serializer with CML outputs can drive an LVPECL clock fanout tree, or an LVDS backplane receiver can be repeated as LVPECL into a PLL. The output is fixed to LVPECL, which provides a larger differential swing (typically 800 mV) than LVDS, useful when driving long traces or multiple AC-coupled loads.
2 Gbps data rate and 630 ps delay — timing budget considerations
Rated for a maximum data rate of 2 Gbps, the part covers common serial standards up to 2.5 Gbps with margin (e.g., 1.25 Gbps XAUI, 2.125 Gbps Fibre Channel). The 630 ps propagation delay is deterministic and adds to the total link latency; in a round-trip timing budget for a clock-forwarded interface, that 630 ps is the per-device contribution. The 0.6 pF input capacitance is low enough that it does not load the driving source appreciably at these frequencies.
Supply and current draw
That is the total current for the whole channel — no separate output bias supply needed. The 8-SOIC package dissipates the heat adequately in still air up to 85°C ambient; if the ambient pushes above 70°C in a confined enclosure, a small airflow or a heatsink on the board plane helps keep the junction below the maximum.
TI lists the SN65LVDS101DR as Active.