2 Gbps signal conditioning for differential links
The SN65LVDS101DGK is a single-channel buffer/reDriver that accepts CML, LVDS, or LVPECL inputs and outputs LVPECL, retiming the signal at up to 2 Gbps. The 630 ps typical delay is the propagation through the reDriver — budget this into the link timing budget, especially in closed-loop clock distribution where skew accumulates across multiple devices. Input capacitance is 0.6 pF, which keeps the load on the upstream driver low — important for maintaining signal integrity at multi-gigabit edge rates on FR4 traces. The 50 mA supply current at 3.0–3.6 V means the total power dissipation in the 8-VSSOP package is under 180 mW, so no special thermal management is needed in most layouts. The 8-VSSOP footprint (3.00 mm width) fits tight channel spacing on a backplane or mezzanine card.