Signal-conditioning buffer for high-speed differential links
It accepts CML, LVDS, or LVPECL inputs and delivers a re-driven LVDS output, making it a straightforward signal-conditioning block for serial links up to 2 Gbps. The 470 ps propagation delay is low enough to fit into most timing budgets without re-tuning the clock tree.
2 Gbps data rate and 0.6 pF input capacitance
The 2 Gbps maximum data rate covers common high-speed serial standards like Gigabit Ethernet, SATA, and PCIe Gen1. The 0.6 pF input capacitance is light enough that it won't load the upstream driver beyond what the trace impedance already presents — important when the buffer sits at the end of a long backplane trace. The 25 mA supply current is the total draw for the single channel; no separate output termination current is included in that figure, so budget the LVDS termination resistors separately.