What this buffer does on a high-speed serial link
It is built for board-level signal conditioning where a fast edge needs to travel across a backplane or a long trace without degrading the eye. The 2 Gbps max data rate covers common serial protocols like Gigabit Ethernet, SATA, and LVDS video links, and the 470 ps propagation delay is low enough that you can budget it into a multi-drop clock distribution without losing margin.
At 2 Gbps the bit period is 500 ps, so the 470 ps delay eats nearly one full bit time. That matters if you are daisy-chaining several buffers in a clock tree — the cumulative delay can shift phase alignment. For a single re-driver in a point-to-point link, the 470 ps is fine; the part is meant to restore signal amplitude and edge rate, not to add zero delay. The 0.6 pF input capacitance is light enough that it does not load the driving source appreciably at these speeds, so you can place it close to the connector without pulling down the upstream driver.
Multi-protocol input — one part for mixed-signal backplanes
The SN65LVDS100DR accepts CML, LVDS, and LVPECL on the input side and always outputs LVDS. That makes it a handy level translator when you are mixing logic families on the same board — say a CML serializer feeding an LVDS backplane, or an LVPECL oscillator driving multiple LVDS fan-out buffers. The 25 mA supply current is modest for a 2 Gbps repeater; it will not stress a 3.3 V regulator rated for a few hundred milliamps.
Package and footprint — 8-SOIC, surface-mount
No need to worry about finding a substitute or stocking up before an EOL cutoff.