Single-channel LVDS repeater for 2 Gbps serial links
It accepts CML, LVDS, or LVPECL input levels and re-drives them as LVDS, making it a bridge part when a board mixes logic families on a serial link. The 2 Gbps data rate covers gigabit Ethernet, serial backplanes, and high-speed ADC/DAC interfaces.
470 ps delay — timing budget for the serial path
The 470 ps propagation delay adds jitter and skew to the serial link. In a 2 Gbps channel (500 ps unit interval), 470 ps is nearly one full bit period of latency — enough to push setup/hold margins if the trace lengths aren't matched. The part is a buffer, not a retimer, so it doesn't clean up jitter from the source; it re-drives whatever it receives. For links that need deterministic delay budgeting (e.g., clock distribution or synchronous serial buses), account for this delay in the timing analysis.
Input flexibility: CML, LVDS, LVPECL — output fixed to LVDS
The SN65LVDS100 accepts three common differential signalling standards at the input: CML, LVDS, and LVPECL. The output is always LVDS. This is useful when a design has a CML or LVPECL source (like a high-speed serializer or FPGA transceiver) but the rest of the board runs LVDS. The 0.6 pF input capacitance keeps loading light on the source, and the 25 mA supply current is modest for a 2 Gbps repeater.
TI lists the SN65LVDS100DGKRG4 as obsolete. No official successor part is published in the lifecycle record.