It is designed to clean up and retime high-speed serial links where the original signal has degraded over a backplane or cable run. The 2 Gbps data rate covers most common serial protocols up to Gigabit Ethernet, SATA, and PCIe Gen 1 line rates. The 470 ps propagation delay is tight enough that a single device adds less than half a unit interval (UI) at 1 Gbps, so timing margin stays intact through one or two repeaters. The 8-VSSOP package (3.00 mm width) fits dense boards where a larger SOIC or MSOP would crowd the routing channel.
Input flexibility and signal compatibility
The SN65LVDS100DGKG4 accepts three common differential signal standards — CML, LVDS, and LVPECL — and outputs LVDS. That means it can sit between a LVPECL clock source and an LVDS receiver without external level-shifting resistors, or clean up a CML serializer output before driving a long backplane trace. The input capacitance is 0.6 pF, which loads the source lightly and preserves signal integrity at multi-gigabit rates.
For production builds that need a dual-source hedge, the base product number 65LVDS100 covers a family of package and temperature variants; the DGK suffix (8-VSSOP) is the common small-outline option.