What this redriver does on a 2 Gbps serial link
Its job is to clean up and retransmit a degraded serial signal — extending the reach on a backplane, cable, or PCB trace without adding a full retimer. The 470 ps propagation delay must be budgeted in the link timing, but the 0.6 pF input capacitance keeps minimal loading on the upstream driver, which matters at these edge rates.
Multi-protocol input — one part for CML, LVDS, or LVPECL
This part accepts CML, LVDS, or LVPECL signal levels on its single input channel and outputs LVDS. That means one BOM line covers multiple interface standards — useful when a design must bridge between a LVPECL oscillator and an LVDS FPGA bank, or between a CML serializer and an LVDS backplane.
Industrial temperature and 8-SOIC footprint
Surface-mount assembly with conventional reflow profiles.
ROHS3 compliant for global shipping.