LVDS signal integrity for 100 Mbps links
2/2 driver/receiver count — channel planning
With two drivers and two receivers on one chip, this transceiver handles two independent full-duplex LVDS channels. That is enough for a bidirectional clock-data pair or two separate unidirectional links, saving board area compared to using two single-channel devices. The 100 Mbps per channel rate is specified as the switching limit, so the aggregate throughput across both channels is 200 Mbps total, though each link is independently timed.
Supply rail and 3.3V system compatibility
No level shifter is needed when the local supply is 3.3V ±5%. The LVDS outputs swing about 350 mV differential, which is standard for LVDS receivers on the other end of the cable.
Place a 0.1 µF decoupling capacitor within 2 mm of each supply pin, and route the differential pairs with 100 Ω controlled impedance. No external termination resistors are required if the receiver is within a few inches on the same board; for cable runs, place a 100 Ω resistor across the receiver inputs close to the pins.