Active-production LVDS transceiver for 400 Mbps point-to-point links
This part is designed for high-speed differential data transmission over controlled-impedance PCB traces or short cable runs, where LVDS provides low EMI and low power dissipation compared to single-ended alternatives at similar data rates.
The 400 Mbps rating is the per-channel data rate, not a combined aggregate. Each of the two driver/receiver pairs can sustain a 400 Mbps serial stream independently. For a typical 8-bit parallel bus serialised with an LVDS serializer, this translates to a 50 MHz parallel clock rate at 1:8 serialisation. The 400 Mbps figure is the minimum guaranteed over supply and temperature — the actual eye opening at the receiver input will be wider at nominal 3.3 V and 25°C, but the spec ensures timing closure across the full industrial range.
The 300 mV margin on each side of 3.3 V covers typical regulator tolerance and ripple. If your board already has a 3.3 V rail for the FPGA or SoC bank, this transceiver shares it — no extra voltage plane needed.
The full-duplex LVDS link maintains its 400 Mbps data rate across the entire temperature band — no derating required. If your application requires 105°C or 125°C ambient, you would need to step up to an automotive-grade LVDS part with a wider Tj range.
This means the part is in ongoing production with normal lead times through authorised distribution.
16-TSSOP package — footprint and layout
The SN65LVDS050PWR is supplied in a 16-lead TSSOP package with 0.65 mm pitch and a 4.4 mm body width. This is a common, widely supported footprint used across TI's LVDS and interface portfolio. No thermal pad or exposed paddle — standard FR-4 PCB with 0.65 mm pitch land pattern is sufficient.