What the 100 Mbps data rate means for the link budget
The 100 Mbps ceiling is the practical limit for point-to-point or multidrop links over twisted-pair or PCB traces up to a few metres; beyond that, signal integrity and skew start to eat into the eye opening. For a backplane or cable interconnect running at 100 Mbps, this part holds margin without needing pre-emphasis or equalisation, which keeps the BOM simple.
LVDS outputs swing roughly 350 mV differential centred around 1.2 V common mode, so the receiver input threshold is referenced to that, not the supply. The driver inputs and receiver outputs are LVTTL/LVCMOS-compatible across the supply range, which means a 3.3 V FPGA, ASIC, or microcontroller can drive and read these pins directly without a level translator. If the system runs a 3.0 V rail, the part still meets full LVDS output swing.