At 100 Mbps each differential pair carries a 100 MHz clock-equivalent signal, so the edge rate is fast enough that PCB layout matters — keep the differential pair impedance around 100 Ω and minimise stub length. Full duplex means the two driver/receiver pairs operate simultaneously, so a single SN65LVDS050D can handle a bidirectional link without needing a direction-control pin or half-duplex turn-around delay. That simplifies firmware and saves a GPIO.
Supply and temperature — the operating envelope
It is not 5V-tolerant on the supply pin, so a 5V-only backplane needs a regulator.