PLL multi-clock generator — six outputs from one reference
The Texas Instruments PLL1708DBQRG4 is a PLL-based multi-clock generator that accepts a single CMOS or crystal input and delivers six synchronized CMOS clock outputs. The 1:6 ratio saves board space and BOM cost in systems that need multiple phase-aligned clocks — think audio codec arrays, multi-channel ADC clock trees, or video timing chains where each converter wants its own master clock.
36.87 MHz ceiling — where it fits the clock tree
Maximum output frequency is 36.87 MHz. That is a natural fit for 48 kHz-based audio sample rates at 256× oversampling (12.288 MHz) or 384× (18.432 MHz), and for lower-speed video pixel clocks in VGA or NTSC/PAL timing. It will not drive a 100 MHz FPGA fabric clock — that is a different tier of PLL. The divider/multiplier block is present (divider yes, multiplier no), so the output frequencies are integer sub-multiples of the input reference, not synthesized up.