PLL Multi-Clock Generator — six outputs from one reference
The Texas Instruments PLL1707DBQR is a PLL-based multi-clock generator that takes a single CMOS or crystal input and delivers six CMOS clock outputs, each phase-locked to the reference. Maximum output frequency is 36.864 MHz, a common ceiling for audio codec master clocks, MCU system clocks, and serial interface timing.
Six clock outputs, one crystal — the 1:6 ratio in practice
The 1:6 input-to-output ratio means a single 36.864 MHz or lower crystal feeds six independent clock trees — useful when a board has multiple ASICs, FPGAs, or codecs each needing a synchronous reference. Input accepts either a CMOS-level square wave or a fundamental-mode crystal, giving the designer flexibility to use an existing oscillator output or a discrete crystal with the on-chip oscillator circuit. All outputs are CMOS, so they drive standard digital clock inputs directly without external level translation.
Temperature grade and package — board-fit notes
Housed in a 20-SSOP package (0.154-inch body width, 3.90 mm), the footprint is compact enough for dense layouts yet hand-solderable for prototyping.