PLL multi-clock generator for audio/video timing trees
The Texas Instruments / Burr-Brown PLL1700EG is a PLL-based multi-clock generator that takes a single TTL reference input and produces six CMOS clock outputs, each phase-locked to the input. It is designed for systems where one master clock must fan out to multiple converters, DSPs, or FPGAs without adding separate clock buffers. The maximum output frequency is 36.87 MHz, which covers the common audio DAC master clock rates (e.g., 12.288 MHz, 24.576 MHz) and lower-speed video pixel clocks. The 1:6 fan-out ratio means one reference oscillator can drive up to six downstream devices, reducing BOM count and board area.
Supply and temperature — dual-rail flexibility with industrial range
The differential input accepts a single-ended TTL reference, while the outputs are CMOS — no external level translation is needed when driving standard CMOS clock inputs on ADCs, DACs, or FPGAs.
NRND — plan the last-time-buy window
This means TI/Burr-Brown will not accept new design-ins, and the part is on a path to end-of-life. For existing production, a last-time-buy order should be placed while supply remains available through independent distribution. For new designs, evaluate the PLL1700 family base number (PLL1700) for any active variants, or consider a pin-compatible clock generator from another vendor — but no direct cross-reference is confirmed here.
20-SSOP footprint — layout checklist
This is a standard surface-mount footprint shared with many other SSOP-20 devices, so PCB layout reuse is straightforward.