It provides eight general-purpose I/O pins controlled over a 100 kHz I²C bus, with push-pull outputs rated for 1 mA source and 25 mA sink per pin. The part includes a power-on reset (POR) feature and a dedicated interrupt output (INT) that asserts when an input changes state, allowing the host controller to poll only on demand.
100 kHz I²C bus and 25 mA sink — sizing the load and the pull-ups
The I²C interface runs at 100 kHz standard mode. For a bus with multiple expanders or other 100 kHz slaves, the total bus capacitance stays under the 400 pF limit for standard-mode timing. The 1 mA source current is lower — if sourcing to a logic input, confirm the input high threshold is met at 1 mA; for driving loads that require sourcing, use an external pull-up to the supply rail or select a different output type.
Interrupt output — saving host cycles on pin-change events
The INT pin (open-drain, active low) pulls low whenever any I/O configured as an input changes from the state last read by the host. This lets the host MCU sleep or service other tasks until a button press, limit-switch closure, or sensor edge occurs. The interrupt is cleared when the host reads the input port via I²C. For battery-powered panels or multi-drop sensor arrays, this interrupt-driven scheme avoids constant polling over the bus.
It is not nearing end-of-life, so production builds can be planned without LTB risk. The part is RoHS3 compliant. For dual-sourcing flexibility, the TCA9536ADTMR is a functional alternative but differs in package (surface-mount), output type (open-drain), and I/O count (4 vs 8) — verify the footprint and drive requirements before substituting.