16-bit I²C I/O expander with interrupt and POR
The PCA9555RGER: It provides 16 push-pull I/O pins that can be individually configured as inputs or outputs, with a 400 kHz maximum clock frequency. An open-drain interrupt output (INT) signals the host when an input state changes, eliminating the need for constant polling. The integrated power-on reset (POR) ensures all I/O channels initialize to a known high-impedance state at startup, preventing uncontrolled output glitches during power sequencing. Each I/O can source 10 mA or sink 25 mA, sufficient for driving LEDs, relays, or small solenoids with external current-limiting resistors.
24-VQFN package — footprint and thermal notes
The PCA9555RGER is supplied in a 24-VFQFN exposed-pad package (supplier device package 24-VQFN, 4 mm × 4 mm body). The small footprint (4x4 mm) suits space-constrained designs, but.
I²C address configuration and bus loading
The PCA9555RGER uses three hardware address pins (A0, A1, A2) to set the I²C slave address, providing up to 32 possible addresses on the same bus (address range 0x20–0x27, plus the three address bits allow 8 addresses per device; multiple devices can share the bus if each has a unique address). At 400 kHz, the total bus capacitance (trace + device input capacitance) must stay under 400 pF to maintain signal integrity.
The base product number PCA9555 covers multiple package variants (including the RGER suffix for the 24-VQFN), so a PCN affecting one variant would typically apply across the family — worth monitoring if the design is long-lived.