MSP430G2102IRSA16T is the entry-level density option in the G2xx line, intended for simple control, sensor interface, and battery-powered applications where every microamp of sleep current matters.
1 KB Flash and 128 B RAM — sizing the firmware budget
With 1 KB of Flash and 128 bytes of RAM, this MCU is not for complex protocol stacks or data logging. The firmware budget fits a single control loop, a few state machines, and a handful of calibration constants. The 128 x 8 RAM array is byte-addressable; watch the stack depth if you use more than a couple of nested function calls. For designs that need more headroom, the MSP430G2xx family scales up to 8 KB Flash and 512 B RAM in the same 16-QFN footprint — a board-spin is not required to move up.
The 16 MHz clock is the top end for this MSP430 core. At that speed the active-mode current draw is around 230 µA/MHz typical, so a continuously running loop pulls roughly 3.7 mA from a 3 V rail. The real value is the ability to burst a calculation and drop into standby (sub-1 µA with the watchdog running) — the 16 MHz lets you finish the work and go back to sleep faster than a slower clock would, saving net energy in duty-cycled sensor nodes.
Package and PCB layout notes for the 16-QFN
The pad is electrically connected to VSS — do not route signals under it. The 10 I/O pins are on the outer perimeter; the USI (I²C/SPI) and the internal oscillator leave the remaining pins for general-purpose use. No external crystal is needed for the internal oscillator, but if you need tighter timing than the ±1% typical RC accuracy, the XIN/XOUT pins can drive a 32 kHz watch crystal or a 4 MHz to 16 MHz ceramic resonator.
On-chip peripherals include a brown-out reset (BOR), power-on reset (POR), a watchdog timer (WDT), DMA, and a PWM-capable timer. The USI module handles I²C and SPI in software-configurable master/slave mode — it is not a full hardware UART, so asynchronous serial requires a bit-banged implementation or an external UART bridge. The DMA controller can move data between memory and peripherals without CPU intervention, useful for streaming ADC samples or SPI transfers while the core sleeps.