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LT1004ID-2-5

TI LT1004ID-2-5 Shunt Voltage Reference, 2.5V ±0.8%, 8-SOIC

MPNLT1004ID-2-5
End of Life

Texas Instruments LT1004ID-2-5 shunt voltage reference, 2.5 V fixed output, ±0.8% tolerance, 20 mA output, 20 ppm/°C typical drift, 8-SOIC package, tube.

$1.58Ref. price · indicative, final on quote
Packaging8-SOIC (0.154", 3.90mm Width)
RoHSROHS3 Compliant
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LT1004ID-2-5 specifications
ParameterValue
Output typeFixed
MountingSurface Mount
Reference typeShunt
Voltage - output (Min (Fixed))2.5V
Output current20 mA
Current - cathode20 µA
Operating temperature-40°C ~ 85°C (TA)
PackageTube
Tolerance±0.8%
Case8-SOIC (0.154\", 3.90mm Width)
Noise - 10Hz to 10kHz120µVrms
Temperature coefficient20ppm/°C Typical

Product details

Active production — no last-time-buy clock

The LT1004ID-2-5: This is not a phase-out line; you can design it into a new BOM without worrying about a forced last-time-buy window.

2.5 V shunt reference — the ±0.8% tolerance and the load ceiling

The LT1004ID-2-5 is a shunt voltage reference with a fixed 2.5 V output and ±0.8% initial tolerance. That 20 mV worst-case spread at 25 °C — for a 12-bit ADC with a 2.5 V reference, the reference error alone consumes about 3.3 LSBs of the accuracy budget before any converter INL or temperature drift. If your system needs tighter than 0.8%, a series reference like the LM4132 (0.05%) is a different topology and pinout; the board spins. The shunt can source or sink up to 20 mA while holding regulation. The practical load limit is lower once you subtract the minimum cathode current of 20 µA — the resistor that biases the shunt must supply both the load current and the reference's own bias. If the total current through the shunt drops below 20 µA, the reference falls out of its specified regulation band. Temperature drift is 20 ppm/°C typical. For a 10-bit ADC that is roughly 2.5 LSBs; for a 16-bit ADC it is 40 LSBs — the drift dominates the error budget at high resolution unless the system is calibrated at temperature.

This is the integrated noise that lands on the reference node; a 16-bit SAR converter sampling at 100 kS/s sees this as roughly 3.2 LSBs of peak-to-peak noise (assuming 6.6× crest factor). If the application needs sub-LSB noise performance, a low-pass filter after the reference output or a lower-noise reference is required.

8-SOIC footprint — standard land pattern, tube delivery

The supplier device package is 8-SOIC. The land pattern is the standard SOIC-8 footprint — same pads as a generic op-amp or comparator. No special stencil aperture or reflow profile beyond the JEDEC standard for a 1.27 mm pitch SOIC.

ROHS3 compliance — no exemption-listed substances

Texas Instruments certifies the LT1004ID-2-5 as ROHS3 Compliant. This means no decaBDE, no phthalates above the threshold, and no RoHS exemption-listed substances. Relevant for EU RoHS and China RoHS declarations at the finished-good level.

Frequently asked questions

What is the closest functional second-source for LT1004ID-2-5 — the LM4040CIM3-3.0/NOPB?

The LM4040CIM3-3.0/NOPB is also a shunt reference, but it is a 3.0 V device in an SOT-23 package with ±0.5% tolerance and 35 µVrms noise. The LT1004ID-2-5 is 2.5 V in an 8-SOIC with ±0.8% tolerance and 120 µVrms noise. They are not pin-compatible — the output voltage, package, and tolerance differ. A board spin and a voltage divider or regulator change are required to substitute one for the other.