Package and board integration — DDPAK/TO-263-5
The LP3856ES-ADJ/NOPB ships in a DDPAK/TO-263-5 surface-mount package (5 leads plus exposed tab). The tab is the output and the primary thermal path — the PCB copper area under it sets the junction-to-ambient thermal resistance. A 1 oz copper plane of at least 1 in² per side keeps the die below the 125°C operating limit at 3A output. The exposed pad requires a solder stencil aperture covering 50-70% of the pad area to avoid voiding. The DDPAK footprint is shared with the TO-263 family, so a single PCB land pattern serves multiple LDO current grades.
Dropout headroom and output adjust range
Maximum dropout is 0.6V at 3A — the input rail must stay at least 600 mV above the set output voltage across load and temperature. With a 5V input rail, the output can be set anywhere from 1.23V up to 6.5V, limited by the 7V absolute input maximum. The adjustable output uses an external resistor divider from the ADJ pin to ground. The 1.23V reference voltage is the minimum output; the divider ratio sets the regulation point. Quiescent current is 4 mA typical, rising to 10 mA supply maximum under heavy load.
PSRR across the frequency band — what 73 dB to 57 dB means
PSRR is specified at 120 Hz as 73 dB typical, rolling off to 57 dB at the same frequency — this is the ripple rejection floor for 50/60 Hz mains ripple and its second harmonic. A 100 mVpp ripple on the input at 120 Hz is attenuated to roughly 22 µVpp at the output at 73 dB, or 140 µVpp at 57 dB. Above 120 Hz the rejection continues to roll off at 20 dB/decade typical for a CMOS LDO architecture. For post-regulation of a switching supply switching at 500 kHz, the PSRR at that frequency is not specified — expect less than 20 dB. A second-stage LC filter ahead of the LDO is recommended if the switching noise floor must stay below 10 µV.