156.25 MHz fixed-frequency reference clock
The LMK62E2-156M25SIAT: That frequency lands exactly on the reference clock for 10GbE, Fibre Channel, and many 25G/100G SerDes PLLs — if your PHY or FPGA requires 156.25 MHz, this oscillator is a direct fit without a PLL multiplier. Output is LVPECL differential, 3.3 V supply. The differential pair drives 50 Ω terminated lines directly — no external bias network needed for AC-coupled paths. The 110 mA max supply current is dominated by the LVPECL output stage; the MEMS core itself draws under 10 mA.
Industrial temperature and stability margin
The silicon MEMS resonator gives better shock and vibration immunity than a quartz crystal — no mechanical spurious modes near the fundamental, and no activity dips across temperature. For a line card that sees fan vibration or shipping shock, the MEMS construction removes one failure mode that quartz oscillators occasionally exhibit.
Package, footprint, and enable pin
6-SMD Module, 5.0 mm x 3.2 mm x 1.1 mm seated height. The Enable/Disable pin (pin 1 on the standard 6-pad layout) lets the system gate the LVPECL output; the oscillator core stays running, so the disable current is 70 mA max versus 110 mA active. The 6-SMD module has no exposed thermal pad — decoupling is a standard 0.1 µF ceramic near the supply pin. The silicon MEMS die is hermetically sealed at the package level; no special handling beyond standard MSL precautions.
RoHS3 compliant per the manufacturer statement.