312.5 MHz timing reference for high-speed serial links
The LMK61E2-312M50SIAR is a fixed-frequency clock oscillator delivering a 312.5 MHz output — a common reference for 10/25/40/100 GbE SerDes, JESD204B converter clocks, and FPGA transceiver banks. The 312.5 MHz rate aligns with the standard 156.25 MHz × 2 multiplier used in many networking PHY and MAC devices, so it directly clocks the PLL reference input without an external frequency doubler.
Supply and temperature margins for the timing tree
The 162 mA supply current is the peak draw at 312.5 MHz; budget this into the 3.3 V rail capacity, especially if multiple oscillators share the same regulator.