Output type and termination — LVPECL signal integrity
LVPECL output delivers a differential signal with typical 800 mV swing across a 50 Ω load to VCC - 2 V. The 100 MHz frequency is a common reference for Ethernet PHYs, FPGAs, and SerDes transceivers.
Supply and power budget — 3.3 V rail, 208 mA max
Operates from a single 3.3 V supply. Maximum supply current is 208 mA when enabled; disabling the output via the Enable/Disable pin drops the current to 136 mA max. That 72 mA saving matters in battery-backed or thermally constrained designs where the oscillator cannot be fully power-gated.
Housed in a 6-SMD Module measuring 7.00 mm x 5.00 mm with a seated height of 1.15 mm. Surface-mount, compatible with standard reflow profiles.
