50 MHz fixed-frequency reference for clock-tree design
The Texas Instruments LMK61E0-050M00SIAR is a fixed-frequency clock oscillator delivering a 50 MHz output from a 3.135V to 3.465V supply rail — the standard 3.3V ±5% range that most FPGA, SoC, and Ethernet PHY clock trees already carry. It draws 162 mA typical, so a dense board with multiple oscillators needs the power budget per node, not just the core voltage rail capacity. The 6-QFM (7x5 mm) module footprint fits into the same land pattern as many 7x5 mm oscillators, simplifying a last-minute swap during BOM consolidation.
Active lifecycle — no design-in risk
This part is safe for new production builds and does not carry the obsolescence risk that forces a board respin mid-lifecycle.
Supply voltage and power considerations
The 3.135V-3.465V supply window means the oscillator runs cleanly off a 3.3V rail with ±5% tolerance — no separate LDO needed if the rail is within that band. The 162 mA supply current is the total draw from that rail; a 3.3V regulator feeding this oscillator plus other loads must budget for the peak, not just the average, to avoid dropout during transient loading.