150 MHz LVPECL reference for high-speed serial links
The LMK60E2-150M00SIAR: That 150 MHz output is the clock source for a 10 Gigabit Ethernet PHY, a PCIe Gen 3 reference, or a high-speed ADC/DAC sampling clock — anywhere the LVPECL differential pair provides the low-jitter edge rates a SERDES needs. The LVPECL output swings 800 mV typical into a 50-Ω to VCC-2V termination, with a common-mode voltage around 2 V. That means the AC-coupling caps and bias resistors on the receiver side follow a standard topology — no exotic termination network needed.
Industrial temperature grade and frequency stability
For a 10.3125 Gbps SERDES, that keeps the reference within the CDR's pull-in range without needing a TCXO. The silicon MEMS resonator eliminates the cold-start frequency overshoot and vibration sensitivity of a quartz crystal — the oscillator starts at the correct frequency within microseconds, and the MEMS element survives 50,000 g shock per the LMK60XX datasheet. For a fanless industrial controller or a base station exposed to fan vibration, that matters more than the ppm number alone.
Supply current and power budgeting
Maximum supply current is 208 mA when enabled, dropping to 136 mA when disabled via the Enable/Disable pin. The disable current of 136 mA is still significant — this is not a low-power sleep mode. If the clock tree needs to power down to save battery, a load switch ahead of the oscillator's 3.3 V rail drops the draw to microamps.
Package footprint and board integration
The footprint matches the standard 7x5 mm XO land pattern — four signal pads on the ends, two center pads for the exposed thermal slug. The LVPECL output pair (OUT, /OUT) should be routed as a 100-Ω differential pair with 50-Ω series resistors placed within 200 mils of the output pins. Surface-mount assembly with standard reflow profile per J-STD-020. The module's moisture sensitivity level is MSL 1 — no bake required before reflow if unsealed within 12 months of manufacture.