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Texas Instruments LMK1D1212RHAT — Clock & Timing ICs

Texas Instruments LMK1D1212RHAT Clock Buffer, 2 GHz

MPNLMK1D1212RHAT
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Texas Instruments LMK1D1212RHAT clock buffer, 2 GHz max frequency, 2:12 differential fanout, LVDS outputs, 40-VQFN exposed pad, tape and reel.

$9.0439Ref. price · indicative, final on quote
Texas Instruments LMK1D1212RHAT datasheet (PDF)
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

LMK1D1212RHAT specifications
ParameterValue
TypeClock Buffer
MountingSurface Mount
Supply voltage1.71V ~ 1.89V, 2.375V ~ 2.625V, 3.135V ~ 3.465V
Frequency - max2 GHz
Operating temperature-40°C ~ 105°C (TA)
InputCML, HCSL, LVCMOS, LVDS, LVPECL
OutputClock, LVDS
PackageTape & Reel (TR)
Case40-VFQFN Exposed Pad
Number of circuits1
Ratio - Input:Output2:12
Differential - Input:OutputYes/Yes

Product details

2 GHz fanout buffer with flexible signal-level support

The Texas Instruments LMK1D1212RHAT is a clock buffer that distributes one of two selectable input clocks to twelve LVDS outputs, supporting a maximum frequency of 2 GHz. The 2:12 fanout ratio means a single device can feed twelve downstream PLLs or SerDes transceivers from a redundant clock source, reducing component count on the board.

Signal compatibility and supply voltage flexibility

Inputs accept CML, HCSL, LVCMOS, LVDS, and LVPECL levels, so the buffer interfaces directly with most common high-speed clock sources without external level translation. All input-to-output paths are fully differential, preserving signal integrity and common-mode noise rejection at multi-gigahertz frequencies.

Frequently asked questions

What input signal types does the LMK1D1212RHAT accept?

The buffer accepts CML, HCSL, LVCMOS, LVDS, and LVPECL inputs, covering the majority of high-speed clock sources used in communications and data-center designs.

What is the maximum frequency the LMK1D1212RHAT can distribute?

The device supports a maximum frequency of 2 GHz on the differential clock path, suitable for 100G/400G line cards, FPGA reference clocks, and SerDes reference distribution.