Clock tree fit for 800 MHz serial links
The LMK05318RGZT is a dual-PLL clock generator with bypass mode, delivering up to 800 MHz on the outputs — enough for 10GbE, PCIe Gen 3/4 reference clocks, or JESD204B SYSREF distribution. The 2:8 input-to-output ratio means two reference inputs feed eight programmable outputs, each independently configurable as CML, HCSL, LVCMOS, LVDS, or LVPECL without external level shifters. Differential signalling on both input and output sides preserves signal integrity over board traces to multiple endpoints — a single device can fan out a clean 156.25 MHz to eight SERDES PHYs.
Surface-mount assembly; the 0.5 mm pitch QFN demands a solder paste stencil with appropriate aperture ratio to avoid bridging on the centre pad.