PLL jitter cleaner with 1.536 GHz ceiling
The LMK04803BISQ/NOPB is a PLL-based jitter cleaner from TI's PLLatinum™ family, designed to scrub phase noise from a reference clock and distribute a clean signal across up to 14 outputs. Its 1.536 GHz maximum frequency makes it suitable for clocking high-speed ADCs, DACs, and RF converters where jitter directly impacts SNR. The 2:14 input-to-output ratio means a single clean reference can feed an entire clock tree — a base station or radar receiver might use one LMK04803 to clock the ADC, FPGA, and backplane logic from a single oscillator, reducing BOM count and board area.
Industrial temperature and supply rails
The supply range of 3.15 V to 3.45 V is tight — a 3.3 V rail with ±5% tolerance stays within bounds, but a noisy or poorly regulated rail may push the PLL out of lock; plan for a low-noise LDO feeding this device. Differential inputs and outputs are supported on both sides, which is the standard for high-frequency clock distribution — LVDS or LVPECL signalling keeps noise coupling low over long board traces. Single-ended LVCMOS is also available for lower-speed fan-out or legacy interfaces.
Supply decoupling should follow the datasheet layout — typically 0.1 µF and 1 µF ceramics per supply pin, placed as close to the package as possible. The tight 3.15 V to 3.45 V supply range means the decoupling network must keep ripple below 50 mV peak-to-peak at the PLL charge-pump frequencies.