400 MHz fanout — the PCIe Gen3 reference clock workhorse
The LMK00334RTVR is a 3:5 differential fanout buffer from Texas Instruments designed for PCI Express and SATA CPU reference clock distribution. It accepts seven input standards — CML, HCSL, HSTL, LVDS, LVPECL, SSTL, and Crystal — and outputs HCSL or LVCMOS. The 400 MHz maximum frequency covers PCIe Gen3 (100 MHz or 125 MHz reference clocks) with margin for Gen4 or Gen5 if the system stays within the 400 MHz ceiling.
Input flexibility — one buffer, seven clock standards
The 3:1 input mux accepts CML, HCSL, HSTL, LVDS, LVPECL, SSTL, and Crystal inputs. That means a single BOM line handles the reference clock fanout for a PCIe root complex (HCSL or LVDS), a SATA controller (CML or LVPECL), and an FPGA transceiver bank (HSTL or SSTL) — no need for separate level translators or dedicated fanout buffers per standard. The differential input-to-output path is fully differential (Yes/Yes), so the buffer preserves the signal integrity of the incoming clock through the fanout tree. The single-ended Crystal input is available for a local oscillator, but the output remains HCSL or LVCMOS — the part does not include a PLL for frequency synthesis.
Supply and temperature — the industrial clock-tree envelope
The 3.15V to 3.45V supply range is a 3.3V nominal rail with ±4.5% tolerance. Staying inside that window matters: the buffer's PSRR is specified at 3.3V, and a rail outside the tolerance injects supply noise that adds jitter to the output clocks.