Active production — 3.1 GHz clock-tree workhorse
The LMK00301ARHSR: Rated for a maximum frequency of 3.1 GHz, this buffer handles the upper end of PCIe Gen 4/5 reference clocks, 100G Ethernet, and JESD204B SYSREF distribution without marginal timing.
3:10 fanout with multi-protocol I/O
Three selectable inputs accept CML, HCSL, HSTL, LVDS, LVPECL, SSTL, or a crystal oscillator — the part translates whichever protocol is on the active input to one of ten HCSL, LVCMOS, LVDS, or LVPECL outputs. The 3:10 ratio means a single device replaces a separate mux plus a fanout buffer, saving board area and reducing the number of active clock-tree components. Both input and output paths are differential-capable, so the part fits into a fully differential clock tree where common-mode noise rejection matters at GHz edge rates.
Supply and thermal — narrow rail, exposed pad
The supply range is 3.15 V to 3.45 V — a tight window that demands a clean, regulated rail. A 3.3 V LDO or switching regulator with low ripple is the typical feed; this is not a part for a wide-VIN bus. Single-circuit device — one buffer/mux/translator channel per package, not a multi-bank array. The base product number is LMK00301.