The LM3S9DN6-IQC80-A2T: The connectivity set is what sets this part apart: Ethernet MAC+PHI, USB OTG, dual CAN 2.0B, plus multiple UART, SPI, I²C, and SSI serial interfaces. On-chip there are 16 analog inputs through a 12-bit ADC, PWM outputs, and a DMA controller to move data without loading the core.
At 80 MHz the ARM Cortex-M3 core delivers about 1.25 DMIPS/MHz, or roughly 100 DMIPS total. That is enough to run a lightweight RTOS, handle Ethernet packet processing at 10/100 Mbps, and still leave margin for application logic. The single-cycle multiply and hardware divide help keep interrupt latency tight for real-time control loops. The 512 KB Flash is organised with 1 KB sectors for the first 4 KB and 4 KB sectors thereafter, which matters when you are managing wear-leveled parameter storage or OTA firmware updates. The 96 KB SRAM is split across two banks, allowing concurrent DMA and CPU access without arbitration stalls in many cases.
Any new design should target the Tiva or a comparable Cortex-M4 part from TI or NXP. Given the obsolete status, buyers should verify stock depth and consider a one-time last-buy for forecasted requirements if the design cannot migrate immediately.
Without those vias, junction temperature climbs fast above 400 mA continuous I/O load. The 1.235 V to 1.365 V core supply means a separate 1.2 V rail is needed alongside the 3.3 V I/O supply — a common two-rail topology for this class of MCU.