80MHz Cortex-M3 with Ethernet and USB OTG
The LM3S9B92-IQC80-C1: It integrates Ethernet MAC+PHY, USB OTG (Host/Device), CAN 2.0B, and multiple serial interfaces (I²C, SPI, SSI, UART, IrDA, LIN, Microwire), making it a single-chip solution for industrial gateways, building automation controllers, and human-machine interfaces that need both wired and local connectivity.
Memory and peripheral profile
256 KB of Flash program memory backed by 96 KB of SRAM gives the application layer room for a real-time operating system kernel, protocol stacks, and data buffers without external memory — the EBI/EMI interface is available if you need to expand beyond that. The 65 general-purpose I/O lines are multiplexed with the peripheral set; the 16-channel 10-bit ADC provides analog input for sensor conditioning without an external converter. On-chip peripherals include a brown-out detect/reset, POR, DMA controller, I²S audio interface, PWM timers, quadrature encoder interface (QEI), and a watchdog timer — the DMA offloads the Cortex-M3 core during high-throughput Ethernet or USB transfers.
An internal oscillator eliminates the external crystal for the core clock, though the Ethernet PHY still requires a 25 MHz reference.
For existing BOM lines, this part is sourced through independent distribution channels on a per-RFQ basis.