Memory sizing for the firmware footprint
128 KB of on-chip Flash is sized for a moderate control-stack image: a TCP/IP stack plus a CANopen node might consume 60–80 KB, leaving room for the application. The 64 KB SRAM is split; the Cortex-M3's bit-banding region can map peripheral registers into the bit-addressable alias space, which simplifies flag handling without extra RAM waste.
The core supply is 1.235 V to 1.365 V.
