80 MHz Cortex-M3 with Ethernet and CAN — what it brings to the BOM
The LM3S8C62-IQC80-A2: The 16-channel, 12-bit ADC and the full set of serial interfaces — Ethernet MAC+PHY, two CAN 2.0B, multiple UARTs, SPI, I²C, and a QEI for motor feedback — mean this single chip can replace a handful of discrete peripherals on the board.
The LM3S8C62-IQC80-A2 is officially marked obsolete. For a production line that already qualifies this footprint and peripheral set, the only path is sourcing verified, date-coded stock through independent distribution.
512 KB of program Flash supports a full embedded TCP/IP stack, a CANopen stack, and a modest application layer without external memory. The 64 KB SRAM handles packet buffers and control data; if the application needs larger DMA buffers or a frame buffer for a display, the external memory interface is absent on this package, so plan the heap accordingly.
100-pin LQFP — footprint and routing
Housed in a 100-LQFP (14x14 mm) with 46 general-purpose I/O, the part is a fine-pitch SMD that routes comfortably on a four-layer board. The exposed pad (if present on the LQFP) should be stitched to ground with vias for thermal relief — the 80 MHz core and Ethernet PHY can draw enough current to need it. No external oscillator is required; the internal oscillator is rated for operation.