The LM3S8C62-IBZ80-A1: The 80 MHz Cortex-M3 core includes a single-cycle multiply and hardware divide.
Ethernet and CAN on one chip — the connectivity story
The LM3S8C62-IBZ80-A1 includes an integrated Ethernet MAC with a dedicated PHY and a CAN 2.0B controller. For a BOM comparison: a design that would otherwise pair a smaller MCU with an external ENC28J60 Ethernet controller and an MCP2515 CAN controller saves about 15-20 mm² of board area and a handful of passive components by using this single-chip approach.
108-BGA package — layout and assembly notes
The part comes in a 108-ball LFBGA package measuring 10x10 mm.
The peripheral list includes a motor-control PWM, a quadrature encoder interface (QEI), a watchdog timer, brown-out detect, and a 16-channel 12-bit ADC. That combination — PWM + QEI + ADC — is a ready-made motion-control signal chain for brushless DC or stepper motor drives. The DMA controller can shuttle ADC results to SRAM without CPU intervention, preserving the 80 MHz core for protocol handling.
The LM3S8C62-IBZ80 (without the -A1 suffix) is the same silicon in the same package.