50 MHz Cortex-M3 with Ethernet and CAN — the dual-network gateway MCU
The peripheral set includes a 10/100 Ethernet MAC+PHY, a CAN 2.0B controller, multiple UART/SPI/I²C serial interfaces, a quadrature encoder interface (QEI), and four 10-bit ADC channels.
Ethernet and CAN simultaneously — no peripheral conflict
Yes, this part can run Ethernet and CAN concurrently. The on-chip Ethernet MAC+PHY and the CAN 2.0B controller are independent peripheral blocks with dedicated DMA channels, so there is no pin-mux conflict or bus contention between the two interfaces. This makes the LM3S8962 a natural fit for industrial gateways that bridge a CAN fieldbus to an Ethernet backbone, or for PLCs that need both a real-time control network and a configuration/SCADA link.
The 256 KB Flash is sized to hold a full embedded web server (lwIP or uIP), a CANopen stack, and the application code with room to spare. The 64 KB SRAM provides a 16 KB to 32 KB TCP window buffer plus the CAN message objects and the RTOS task stacks. If the application needs more data logging or display buffering, the external memory interface (EMIF) is not present on this package variant — the on-chip RAM is the limit. For most single-chip gateway and controller designs, this memory partition is well balanced.
100-LQFP (14x14 mm) — board-level integration notes
For dual-sourcing resilience, the Stellaris family includes several pin-compatible siblings with varying memory and peripheral mixes — the LM3S8962 is the Ethernet+CAN variant in the 100-pin LQFP footprint.
The active lifecycle means there is no supply-chain urgency driven by an EOL clock — but the part is single-sourced from Texas Instruments, so a confirmed quote is the prudent step before committing a BOM line.