The LM3S8933-EQC50-A2T peripheral set includes Ethernet MAC+PHY, CAN, multiple UART/SPI/I²C, and a 4-channel 10-bit ADC.
50 MHz Cortex-M3 — enough headroom for a real-time control loop
At 50 MHz the ARM Cortex-M3 core delivers about 1.25 DMIPS/MHz, so the LM3S8933 can handle a PID loop at several kHz while servicing Ethernet and CAN traffic. The 64 KB RAM gives room for a moderate TCP/IP buffer pool alongside the application heap. If your control algorithm needs deterministic interrupt latency, the nested vectored interrupt controller (NVIC) on the M3 handles 12 cycles from assertion to the first instruction of the handler — no software prioritisation needed.
Ethernet and CAN on a single chip — the connectivity argument
The Ethernet MAC includes an integrated 10/100 PHY, so you only need a magnetics module and RJ45. CAN is the 2.0B controller with 32 message objects. For a gateway that bridges a CAN fieldbus to an Ethernet backbone, this part is a natural fit — one MCU handles both sides without a second processor.
That puts this part squarely in the surplus and independent-distribution channel. If your BOM still calls for it, availability is limited to whatever stock remains in the pipeline — no new factory orders. The 100-LQFP (14×14 mm) package and 2.25–2.75 V supply rail are specific enough that a drop-in replacement from another vendor is unlikely without a board spin. For a production line that cannot requalify, securing the remaining inventory through a broker is the practical path.
Package and temperature — the physical fit
The 100-LQFP (14×14 mm) body with 0.5 mm pitch is a common footprint for this class of MCU.