Stellaris LM3S6965 — what this Cortex-M3 brings to a connected control design
The LM3S6965-IBZ50-A2: Connectivity options cover Ethernet, I²C, IrDA, Microwire, QEI, SPI, SSI, and UART/USART, plus a 4-channel 10-bit ADC.
Any remaining stock is held by independent distributors and surplus brokers. If the design is still in development, migrating to a current-production Cortex-M3 or Cortex-M4 with Ethernet MAC and similar memory sizing is worth evaluating for long-term supply.
Package and layout — 108-BGA (10x10 mm)
The 0.8 mm ball pitch is manageable with standard SMT assembly, but the board must be designed with via-in-pad or microvia escape routing for the inner balls.
Firmware bring-up note
The LM3S6965 boots from internal Flash with BOOT0 strapped low; the JTAG/SWD debug port stays alive even with the watchdog armed. The 50 MHz PLL requires the Flash wait state bumped to 1 before raising the core clock above the default, or the first branch instruction will hard-fault. The internal oscillator is available, but for Ethernet operation an external 25 MHz crystal is typically needed to clock the MAC.