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Texas Instruments LM3S617-EQN50-C2T — Microcontrollers & Processors (MCU / MPU / DSP)

LM3S617-EQN50-C2T Stellaris ARM Cortex-M3 MCU, 50 MHz, 32 KB Flash

MPNLM3S617-EQN50-C2T
NRND

Texas Instruments Stellaris® ARM® Cortex®-M3S 600 series, LM3S617-EQN50-C2T, 32-bit single-core MCU, 50 MHz, 32 KB Flash, 8K x 8 RAM, 30 I/O, 48-LQFP (7x7), -40°C to 105°C, 3V to 3.6V supply.

$4.6207Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

LM3S617-EQN50-C2T specifications
ParameterValue
SeriesStellaris® ARM® Cortex®-M3S 600
MountingSurface Mount
Oscillator typeInternal
Program memory typeFLASH
Voltage - supply (Vcc (Vdd))3V ~ 3.6V
Operating temperature-40°C~105°C(TA)
Speed50MHz
PackageTape & Reel (TR)
RAM size8K x 8
Core size32-Bit Single-Core
PeripheralsBrown-out Detect/Reset, POR, PWM, WDT
ConnectivityMicrowire, SPI, SSI, UART/USART
Number of i (O)30
Core processorARM® Cortex®-M3
Case48-LQFP
Data convertersA/D 6x10b
Program memory size32KB (32K x 8)

Product details

The LM3S617-EQN50-C2T is a 32-bit ARM Cortex-M3 microcontroller from the Stellaris 600 series, running at 50 MHz. It carries 32 KB of Flash program memory and 8 KB of SRAM, with 30 general-purpose I/O lines and a 6-channel 10-bit ADC.

At 50 MHz, the Cortex-M3 core executes a single-cycle multiply and a hardware divide, which matters for PID loops and sensor fusion math. The 8 KB SRAM limits the data buffer for UART or SPI streams — expect to offload larger logs to external serial Flash or handle them in the 32 KB program space.

The LM3S617-EQN50-C2T carries an NRND status. For new designs, look at current-generation parts in a similar 48-LQFP pin count.

The 6-channel 10-bit ADC samples analog inputs for current sensing or potentiometer feedback. All 30 I/O are brought out on the 48-LQFP; verify your pin allocation against the datasheet pinout before layout.

Frequently asked questions

What is LM3S617-EQN50-C2T's core speed?

The ARM Cortex-M3 core runs at 50 MHz, with a single-cycle multiply and hardware divide for efficient control-loop math.