The LM3S5K36-IQR80-C5: The 80 MHz Cortex-M3 delivers roughly 1.25 DMIPS/MHz, so you are budgeting about 100 DMIPS of integer throughput. That is enough for a sensor-fusion loop running at 10 kHz with headroom for the protocol stack (CANopen or Modbus RTU). The single-cycle multiply and hardware divide help keep interrupt latency predictable — important when the PWM or QEI peripheral is driving a motor phase.
The 128 KB Flash (128K x 8) and 24 KB SRAM (24K x 8) set the firmware and data-buffer ceiling. A typical CANopen node with a bootloader, a few hundred lines of application code, and a modest data table fits comfortably. If your application requires a full USB host stack, a large lookup table, or over-the-air update staging, you will need to check the image size against this budget before committing the BOM line.
TI has ended production; there is no active last-time-buy window. New supply is available only through independent distribution and surplus channels.